Wing of a dragonfly

Glasswing Interconnect Solutions

The GW-500 Quad Glasswing PHY is the first PHY to utilize Chord™ Signaling, an innovative new PHY technology. Glasswing uses CNRZ-5 Chord Signaling, a form of signaling that fits in the space between single-ended and differential signaling. Chord Signaling can make almost every interface better by getting more bits through with lower power and fewer pins without sacrificing margins.

Key Features

GW-500 supports the following key features:

  • 500 Gbps of bi-directional throughput
  • 1.04 pJ/bit or 1 Tbps per watt
  • Beachfront bandwidth: 208 Gbps/mm die edge
  • 6dB insertion loss budget (40+ mm on GZ-41 substrate)
  • Standard 150 μm bump pitch; NO interposer required!
  • Low, fixed latency
  • Native BER of 1E-15
  • Option Forward Error Correction (FEC) block extends BER well above 1E-20
  • PRBS pattern generators and loopback modes
  • Protocol agnostic
  • Built-in eye scope and advanced diagnostics

Product Benefits

Uses the Chord Signaling Code CNRZ-5

This code has inherently higher throughput per pin than equivalent NRZ solutions and inherently lower power per bit than equivalent PAM-4 solutions. The code allows Glasswing to get more bits through with less power.

Excellent Diagnostic Capabilities

The integrated eye scope allows non-destructive testing of in-service links and test-equipment level debug of out-of-service links.

Supports Large MCMs

The 40+ mm reach and corner turning capability of the Glasswing allows MCMs up to 70mm to be efficiently supported. This allows a complex collection of dies to be integrated on a package substrate or organic interposer for a System in Package (SiP) solution.

Delivers Massive Bandwidth

Glasswing can be tiled in both directions to deliver terabits of bandwidth between dies.

General Applications

  • Divide your chip into multiple dies or chiplets
  • Implement each portion of your solution in the most appropriate semiconductor process
  • Avoid the use of difficult and costly silicon interposer technology in your product
  • Reduce the size of your largest die in order to enhance its yield or address reticle size limits
  • Create an ecosystem of interconnecting chiplets with common interfaces

Specific Applications

  • Tiling on CPUs, DSPs, or AI accelerator processors
  • Separating the I/O subsystem function on the Ethernet or OTN switch core
  • Separating the radio interface from the processing subsystem in a high bandwidth 5G system
  • Separating Analog to Digital Converters (ADCs) from a digital subsystem
  • Separating a custom analog subsystem from a digital subsystem

The following is available to support your evaluation and development with Glasswing.

Product Brief

GW16-500

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Product Brief

GW12-500-USR

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Datasheet

GW16-500-USR

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Routing Guidelines

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Characterization Report

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Verilog Customer Model

Application Note

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The following is available to support your evaluation and development with Glasswing

KEYE simulation software

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Please note an NDA and client password may be required for access, Contact Us for more information